It’s all hands on deck in the infrastructure world right now, especially when it comes to silicon. Accelerated computing and AI have made chips more central than ever to everything from hyperscale data centers to scientific supercomputers. But as demand rises, manufacturing capacity isn’t the only bottleneck. Another impediment is the time and talent required to design and verify these increasingly complex chips before they ever reach the fab.
That friction is what Cadence, an electronic design automation (EDA) software provider, is addressing with today’s launch of its ChipStack AI Super Agent, a new agentic AI system designed to automate front-end chip design and verification and compress some of the most lengthy and repetitive work in chip development.
ChipStack AI Super Agent is focused on the front end of the chip development flow, where design intent is translated into register-transfer level (RTL) code, testbenches, and verification plans. This front end is where schedule risk, or the potential for delays caused by design and verification rework, can accumulate before manufacturing begins. Compounding the problem, Cadence estimates that by the end of this decade, the industry will face a shortage of hundreds of thousands of chip design and verification engineers.
The ChipStack AI Super Agent interface (Credit: Cadence)
To understand how the company is approaching this problem with agentic AI, AIwire spoke with Matt Graham, senior group director of verification software product management at Cadence, and Kartik Hegde, senior group director of agentic AI and ChipStack at Cadence, about what this new tool can help engineers accomplish and how it fits into existing design flows.
How the ChipStack AI Super Agent Works
“The ChipStack AI Super Agent that we’re announcing here is really our first foray into automatically generating the intellectual property — the design, test harnesses, and regression suites — that are required during pre-silicon development, before a design moves into manufacturing,” Graham told AIwire. “We really think it’s a first of its kind.”
The ChipStack AI Super Agent operates inside the front-end workflows that chip designers and verification engineers already use. Rather than replacing Cadence’s simulation, formal verification, and analysis engines, it sits on top of them, generating and orchestrating the inputs those tools require while interpreting their outputs. This orchestration role is where much of the automation happens. Instead of prompting an AI model to produce isolated snippets of code, the system coordinates multiple agents that can generate RTL, assemble testbenches, define verification plans, execute simulations, parse logs, diagnose failures, and iterate on fixes. This mirrors the way human engineers work, but at a much faster pace. According to Hegde, making that approach viable required training the agents to have a deeper understanding of the design process itself.
“What does it take to convert an LLM agent into an actual chip designer? To do that, we have poured three things into the recipe. The first one is to give the model the ability to understand the underlying chip design and its intent. We call this the Mental Model. This is the way the agent extracts the knowledge of what this chip is supposed to do,” explained Hegde. “Second, we have given it expert-crafted flows on the knowledge of how to design and how to do verification, so the agent is now capable of formal and simulation verification. Third, we give it the ability to run EDA tools, teaching it how to call Cadence’s principled software solutions like simulators and formal engines.”
The Mental Model (Credit: Cadence)
The “Mental Model” Hegde mentions is the foundation of the software. It is created by ingesting specifications, RTL code, and other design artifacts, combining traditional static analysis (using compilers and parsers Cadence has refined over decades) with LLM-based reasoning to add contextual information that static tools do not provide on their own. For example, while a compiler can identify a port or interface, an LLM can help determine its function by examining naming conventions, documentation, and surrounding logic. The company says this Mental Model acts as a grounded source of truth that agents must reference when generating code or tests, helping prevent the hallucinations that probabilistic models are known to have. Once a Mental Model is established, the ChipStack AI Super Agent can drive an iterative design and verification loop. In a typical verification workflow, the system uses the model to generate a test plan, writes the associated test code, runs Cadence simulation or formal tools, and analyzes the results. If a test fails, the agent parses logs, proposes a root cause, and applies fixes before rerunning verification, either autonomously or with an engineer guiding the process.
Hegde described this as an intentionally human-in-the-loop approach. While the system can run end-to-end, it is designed to let engineers intervene, provide feedback, or adjust assumptions at any stage. “The user is still in the driver’s seat,” Hegde said. “It’s kind of like a senior engineer working with a new engineer to help them complete the tasks.”
The ChipStack AI Super Agent relies on frontier LLMs rather than models trained from scratch. As deployment flexibility is critical for adoption, Cadence supports both cloud-based and on-prem deployments, reflecting the data privacy, intellectual property, and security concerns common in semiconductor development. Customers can run the system using commercially available frontier models accessed through standard APIs, while Cadence works with model providers to fine-tune those systems for chip design and verification tasks.
Productivity Gains
For chip designers and verification engineers, the appeal of agentic AI is that it can absorb repetition and save a great deal of time in chip projects. Cadence says early deployments of the ChipStack AI Super Agent are showing order-of-magnitude improvements in this area. Across design coding, testbench generation, test plan creation, regression orchestration, and failure analysis, customers are reporting productivity gains of up to 10x, according to the company.
(Credit: Cadence/ChipStack)
In internal evaluations and customer pilots, tasks that once took days or weeks have been compressed into hours, Cadence claims. The company cited examples, including formal verification cycles reduced from multiple weeks to hours, and test plan creation accelerated from weeks to same-day outputs. In one demo Hegde presented, a verification workflow that would typically take a full workday was completed in under 20 minutes.
Several early customers have validated those claims. FPGA maker Altera reported significant reductions in verification efforts on complex designs, while AI and accelerator vendors, including Nvidia, Qualcomm, and Tenstorrent are evaluating or deploying the system across production workflows. Tenstorrent reported significant time savings in formal verification during early evaluations of the ChipStack AI Super Agent, including deployments on its own on-prem hardware.
“ChipStack greatly improved the efficiency of our formal verification efforts,” said Daniel Cummings, principal engineer of RISC-V Cores at Tenstorrent, in a release. “During a three-month evaluation on three critical design blocks, it reduced verification time by up to 4X. Running the agent on Tenstorrent hardware also demonstrated our ability to deliver the high-performance, on-prem inference needed for production-scale LLM workloads.”
How It All Came Together
Although the ChipStack AI Super Agent is Cadence’s first major agentic AI product launch, the work behind it has been building for years. Graham emphasized how Cadence’s roots are firmly planted in EDA, where accuracy is imperative and mistakes discovered after manufacturing can be catastrophic.
Kartik Hegde and Matt Graham (Credit: Cadence)
“Anytime we design a chip, it needs to be 100 percent correct before it goes to manufacturing,” Graham said. Over time, he says, those same principled simulation and optimization engines that enable this precision have expanded beyond chips into printed circuit boards, multiphysics analysis, data center systems, and even molecular and biological simulation. The common thread, Graham says, is the strength of this computational software, built on a foundation of math and computer science, designed to improve engineering productivity without sacrificing accuracy.
That emphasis on deterministic engines also explains Cadence’s approach to incorporating AI. The company began applying machine learning and reinforcement learning roughly six years ago, first to optimize the performance of its existing tools. Then came Cadence’s acquisition of ChipStack in late 2025. Co-founded in 2023 by Hegde, who was also the company’s CEO, ChipStack was built specifically to tackle front-end design and verification bottlenecks using AI. Hegde, who previously worked as a chip designer and later completed a PhD focused on computer architecture and machine learning, said the startup’s goal was to reduce the time it takes to build chips by accelerating the most labor-intensive stages.
Both Graham and Hegde credit their own backgrounds as design and verification engineers in shaping the system’s development. Rather than aiming for full autonomy from the outset, they focused on encoding the kinds of practical decisions engineers make every day, from interpreting specifications to choosing verification methods, managing regressions, and debugging failures. That focus on practical engineering decisions also shaped how quickly Cadence moved after acquiring ChipStack. Just three months after the deal closed, the two teams have combined their strengths, Cadence’s EDA infrastructure with ChipStack’s agentic AI work, to deliver the ChipStack AI Super Agent.
“Technology grows either through very aggressive and agile startups or through investment from established companies in a particular area. And in this case, I think the right mix of knowledge and aggressiveness came together,” Graham said.
“With this acquisition, I think Cadence got two key things. One is the core innovations we have done, like the Mental Models and expert flows that I talked about. Second, we have a world-class team, which continues to power this,” Hegde said. “Together, the mixture of some of our core innovations and a very high-quality team was the key accelerant to getting this out.”
Looking Ahead
While the ChipStack AI Super Agent is not yet a fully autonomous system, Graham describes it as an early step in that direction.
(amgun/Shutterstock)
“Our ultimate goal is to get to this full autonomous chip design. This is our moonshot. We want ‘specification goes in one side, microchip falls out the other,’” Graham said. “The reality is that we’re probably a decade or more away from approaching that, if autonomous driving is any indication of how long it takes to really get there on a broadly deployed scale.”
For now, Cadence is focused on specific front-end use cases where autonomy can be applied safely and productively. Engineers can allow the agent to run end-to-end, but they can also intervene at any stage to guide decisions, adjust assumptions, or validate results. Over time, Cadence expects that balance to shift as confidence in agentic AI grows and as the system is exposed to a wider range of designs and use cases. The executives also suggested that the architecture behind the ChipStack AI Super Agent is designed to scale beyond its initial scope. The same Mental Model and agent orchestration approach used today for front-end design and verification could eventually extend into other phases of chip development, such as integration, implementation, and signoff.
At its core, the main expectation of the ChipStack AI Super Agent is consistency. Instead of replacing engineers and their hard-earned knowledge, the system promises to lessen their exhaustive manual work while maintaining meticulous verification standards. As Graham puts it, “The AI agents aren’t going to suffer from fatigue. It’s going to be just as thorough on page 500 as it was on page one of a specification.”
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